SoC STA/Timing Engineer (Staff/Sr Staff)
Qualcomm Incorporated (company site, opens in a new tab)7–15 yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted on 9 Sept
Reach people at Qualcomm Incorporated
People at this company you can reach
Log in to see who works here
Create a free account or log in to see the people at Qualcomm Incorporated you could write to:
- Recruiters & HR
- People in this function
- Work addresses
Your match
Against your primary resume
Log in to see your match score
Create a free account or log in to unlock your CV match score across:
- Role fit
- Experience
- Industry relevance
Protocol Intelligence
How competitive this role is
Competition
Background fit
Strictness
Log in to see why each signal reads the way it does.
Job description
Structured overview of role & requirements
About This Role
- Lead STA (Static Timing Analysis) setup, convergence, and signoff for complex multi-mode, multi-voltage SoC and subsystem designs.
- Perform timing analysis and debugging across multiple PVT (Process, Voltage, Temperature) conditions using tools such as PrimeTime and Tempus, including ECO (Engineering Change Order) timing flows and logical equivalence checks.
- Develop and optimize STA/PD flows and timing methodologies using scripting (TCL/Perl/Python) and collaborate cross-functionally with design, DFT, synthesis, technology, CAD, and physical implementation teams.
Minimum Requirements
- 7 to 15 years of relevant experience in STA or hardware engineering roles.
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field with at least 6 years experience (or Master's with 5 years, PhD with 4 years).
- Hands-on expertise with STA tools such as PrimeTime and Tempus and scripting skills in TCL, Perl, and Python.
- Familiarity with ASIC backend flows ICC2 and Innovus, and knowledge of STA fundamentals including AOCV/POCV, CTS, timing constraints, and signal integrity (cross-talk, parasitic extraction).
Ideal Candidate Profile
- Experienced engineer able to drive timing closure at both chip-level and hard-macro level in complex SoC environments.
- Capable of independently developing and automating STA and power-device flows and optimizing timing methodologies across technology nodes.
- Skilled at mentoring junior engineers and effectively collaborating across multiple hardware design and verification disciplines in a high-tech ASIC development setting.