Principal DFT Engineer
Synopsys (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted on 7 Sept
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Job description
Structured overview of role & requirements
About This Role
- Lead and oversee execution of scan insertion, ATPG flows, and scan STA for complex ASIC IP designs, managing a team of DFT engineers.
- Collaborate closely with RTL, Verification, and cross-functional teams to integrate DFT requirements early and optimize test coverage and timing closure.
- Drive continuous improvements in DFT methodologies and automation using AI tools to enhance efficiency and reduce time-to-market.
Minimum Requirements
- 8+ years of relevant experience, including technical leadership of DFT execution for IP projects.
- BS/MS in Electrical Engineering or Electronics and Communication Engineering.
- Proven experience with DFT methodologies including scan insertion, ATPG for complex ASIC designs.
- Proficiency with EDA tools such as Spyglass DFT and scan STA analysis suites.
Ideal Candidate Profile
- Experienced technical leader comfortable managing DFT teams and collaborating across design, verification, and program management.
- Skilled in diagnosing and resolving DFT issues throughout multiple project phases, with demonstrated expertise in DFT flows.
- Familiar with applying AI tools and scripting to automate design and test flows, with a strong foundation in digital logic design and verification principles.