Principal ASIC Verification Engineer - DDR/LPDDR
Synopsys (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 35–65 LPA
Posted on 7 Sept
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Job description
Structured overview of role & requirements
About This Role
- Lead a team of verification engineers through full IP verification cycles for DesignWare IP cores, from test plan definition to coverage closure and signoff.
- Build, evolve, and scale SystemVerilog/UVM verification environments for synthesizable IP cores, including DDR/LPDDR memory controllers and serial interface protocols.
- Analyze and drive functional and code coverage metrics to closure, manage regression infrastructure, and collaborate with RTL designers and architects to align verification scope with design intent.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering.
- 8+ years of hands-on verification experience, with proven leadership in verification team management and IP project delivery.
- Strong expertise in SystemVerilog/UVM testbench development and verification methodologies for IP cores, including writing test plans, checkers, and assertions.
- Experience verifying serial interface protocols and memory controllers with knowledge of DDR or LPDDR protocols; Work Experience Required: 8+ years.
Ideal Candidate Profile
- Experienced in leading verification teams in a complex IP verification environment with high production volume impact.
- Strategic thinker who can translate coverage analysis into actionable plans and drive verification closure efficiently.
- Technical expert capable of refactoring and evolving verification environments for scalability and reliability, comfortable collaborating across global teams and interfacing with architects and designers.