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Tier-1 brand and Bangalore metro increase competition, but niche ASIC verification skills reduce the applicant pool.
Specialized ASIC verification skills and DDR protocol knowledge are not easily transferable across industries.
Explicit 8+ years, mandatory SystemVerilog/UVM and DDR verification experience make filters highly strict.
Lead a team of verification engineers through full IP verification cycles for DesignWare IP cores, from test plan definition to coverage closure and signoff.
Build, evolve, and scale SystemVerilog/UVM verification environments for synthesizable IP cores, including DDR/LPDDR memory controllers and serial interface protocols.
Analyze and drive functional and code coverage metrics to closure, manage regression infrastructure, and collaborate with RTL designers and architects to align verification scope with design intent.
Bachelor's or Master's degree in Electrical Engineering or Electronics and Communication Engineering.
8+ years of hands-on verification experience, with proven leadership in verification team management and IP project delivery.
Strong expertise in SystemVerilog/UVM testbench development and verification methodologies for IP cores, including writing test plans, checkers, and assertions.
Experience verifying serial interface protocols and memory controllers with knowledge of DDR or LPDDR protocols; Work Experience Required: 8+ years.
Experienced in leading verification teams in a complex IP verification environment with high production volume impact.
Strategic thinker who can translate coverage analysis into actionable plans and drive verification closure efficiently.
Technical expert capable of refactoring and evolving verification environments for scalability and reliability, comfortable collaborating across global teams and interfacing with architects and designers.