Lead Software Engineer
Candescent (company site, opens in a new tab)4–6 yrsNoidaOn-siteDirect career pageEst. 15–28 LPA
Posted on 8 Sept
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Job description
Structured overview of role & requirements
About This Role
- Own design, development, verification, and deployment of Verification IP (VIP) for layered protocols.
- Create and debug functional verification test environments using SystemVerilog/UVM.
- Collaborate cross-functionally and interact closely with customers to adapt to new protocols and technologies.
Minimum Requirements
- 4 to 6 years domain experience in functional verification or related area.
- Proficiency with SystemVerilog/UVM for test environment creation and debugging.
- Experience with layered protocols such as UCIe, PCIe, CXL, Ethernet, or Ualink.
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering.
Ideal Candidate Profile
- Experienced with VIP development and usage, demonstrating strong digital electronics and programming fundamentals.
- Ability to quickly learn new verification technologies and protocols independently.
- Skilled in cross-functional communication and customer interaction in fast-paced technology environments.