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Tier-1 brand and metro boost competition, but niche senior ASIC DV specialization limits candidate pool.
High because ASIC/UVM verification skills are highly domain-specific and less transferable across industries.
High due to 10+ years requirement, mandatory UVM/SystemVerilog expertise and protocol/IP verification experience.
Lead and oversee IP/Block and Subsystem level verification from test plan creation through sign-off, ensuring first-pass success.
Develop and manage SystemVerilog/UVM testbenches and environments for ASIC IP/Block/Subsytem verification.
Mentor and lead a team of verification engineers while collaborating globally on technical initiatives.
10+ years experience with M.S./M.Tech or BS/BE in Electronics.
Expertise in IP/Block/Subsystem level verification including test plan and UVM environment development.
Experience with AMBA protocols (AXI/AHB), PCIe, NVMe, DDR protocols and controllers.
Proficient in RTL debugging, assertions, functional and code coverage analysis, and SystemVerilog/Verilog languages.
Proven experience leading teams of verification engineers (preferably 5+ members) and driving IP/Block verification to completion.
Strong technical expertise in ASIC verification with hands-on knowledge of PCIe, NVMe, DDR controllers.
Comfortable working in cross-functional, multinational teams aligning on verification strategy and execution.