Principal Engineer - ASIC DV
Eightfold AI (company site, opens in a new tab)10+ yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted on 8 Sept
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Job description
Structured overview of role & requirements
About This Role
- Lead verification for IP/Block and Subsystem including test plan creation, SystemVerilog/UVM testbench development, and verification sign-off.
- Manage and mentor a team of verification engineers ensuring first-pass product success against verification coverage and sign-off criteria.
- Collaborate with domain specialists across global locations on core technical initiatives.
Minimum Requirements
- M.S./M.Tech or BS/BE in Electronics with 10+ years of experience.
- Expertise in IP/Block/Subsystem level verification using SystemVerilog and UVM methodologies.
- Experience with AMBA protocols (AXI/AHB) and storage/controller protocols such as PCIe, NVMe, DDR including working on DDR/PCIe/NVMe controllers or similar IPs.
- Proven skills in building verification plans, UVM environment and test benches, RTL debugging, scoreboard, assertions, functional and code coverage analysis.
Ideal Candidate Profile
- Experienced in technically leading IP/Block verification projects from start to completion with strong leadership of verification teams (preferably managing teams of 5+ engineers).
- Strong domain expertise in RTL front-end verification and protocols including NVMe; familiarity with security aspects like boot, ROM, firmware protection is a plus.
- Comfortable working in globally distributed cross-functional teams with good communication skills to influence technically and operationally.