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Tier-1 brand and Bangalore location raise competition, but niche EDA specialization narrows the candidate pool.
EDA tools and VLSI expertise heavily industry-specific, limiting cross-industry transferability.
Explicit 3–10 years and mandatory SKILL/Python/TCL plus EDA/VLSI expertise increases shortlisting strictness.
Design, develop, and support custom design infrastructure, EDA methodologies, and automation solutions for semiconductor testchip development across advanced technology nodes.
Drive end-to-end enablement of testchip integration, custom layout design, E-Test structures, design libraries, and verification flows to accelerate process technology development and silicon readiness.
Develop and maintain automation frameworks using SKILL, Python, and scripting languages; enable and validate CAD environments, version-control systems, and database infrastructures.
Bachelor's or Master's degree in Electronics Engineering, Computer Science, or related field.
3-10 years of experience in CAD software development, VLSI, or Design Enablement.
Proficiency in SKILL, Python, and TCL/PERL programming; knowledge of VLSI concepts and EDA tools (Cadence/Synopsys).
Knowledge of custom layout, data structures, algorithms, and software optimization.
Experienced engineer with strong background in CAD software development and EDA tool methodologies related to semiconductor testchip development.
Capable of working collaboratively with cross-functional teams including design, process, technology development, reliability, and validation.
Skilled in developing automation frameworks and validating CAD environments to support scalable methodologies for full-chip integration and silicon characterization.