Senior Staff Verification Engineer, High-Speed Interconnect
Synopsys (company site, opens in a new tab)7+ yrsHyderabadOn-siteDirect career pageEst. 28–50 LPA
Posted on 6 Sept
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Job description
Structured overview of role & requirements
About This Role
- Own end-to-end verification of high-speed interconnect IP blocks (UCIe, PCIe, or DDR) including test planning, UVM testbench development, coverage closure, and sign-off.
- Debug complex RTL and testbench failures using Synopsys Verdi and other industry tools, translating protocol specs into executable test plans and assertions.
- Mentor junior engineers on UVM methodology and protocol understanding; collaborate cross-functionally on bug triage, ECO analysis, and bring-up readiness.
Minimum Requirements
- 7+ years of ASIC or SoC design verification experience with at least 3 years focused on protocol-heavy IP.
- Proficient in at least one of these protocols: PCIe, UCIe, or DDR, with the ability to read protocol specs and build compliant testbenches.
- Strong expertise in UVM methodology, SystemVerilog (including OOP and SVA), and debugging tools such as Synopsys Verdi.
- Bachelor's or Master's degree in Electronics, VLSI, Electrical Engineering, or related field.
Ideal Candidate Profile
- Experienced in developing maintainable, reusable verification environments that serve multiple product generations.
- Skilled at root-cause debugging of complex intermittent regressions and effectively communicating technical issues to both design and architecture teams.
- Takes ownership of verification as a product, ensuring thoroughness, documentation, and knowledge transfer to enable cross-team success.