Back
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Niche ASIC verification reduces competition but Tier-1 brand and Bangalore metro increase candidate density.
ASIC/UVM/SystemVerilog expertise makes background highly domain-specific and hard to transfer across industries.
10+ years and deep SystemVerilog/UVM and SoC verification mandates make filters highly strict.
Develop and execute comprehensive ASIC/SoC verification plans focused on functional correctness, robustness, and quality assurance.
Design and enhance SystemVerilog (OVM/UVM) testbenches and reusable Verification IP components for complex SoC architectures.
Collaborate with internal teams and external customers to ensure coverage closure and debugging using advanced verification methodologies and tools.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10 years of experience in SoC/IP verification.
Strong expertise in SystemVerilog, UVM, ARM-based SoC architectures, and relevant protocols (AXI/AHB/APB).
Proficiency in scripting (Python, Perl, Shell) and experience with power-aware verification (UPF/CPF).
Experienced in building reusable, scalable testbench architectures and applying advanced verification methodologies including coverage-driven verification.
Familiar with GLS, timing verification, debug, and applying AI/ML techniques for verification improvement.
Capable of independently driving verification projects involving complex SoC designs and cross-functional collaboration.