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Strong employer brand, metro location, and mid-level experience increase candidate competition.
Role requires niche semiconductor foundry, PDK and EDA expertise, limiting cross-industry transferability.
Explicit 2–4 years and mandatory PDK/DRC/LVS/Spice expertise create strict filtering criteria.
Own validation, deployment, and maintenance of foundational PDK components for advanced semiconductor nodes.
Conduct technology studies benchmarking standard cell, SRAM, custom circuits, and interconnect to optimize power, performance, and area.
Design, develop, and maintain scripts and automation flows for PDK enablement, validation, and analysis while collaborating with DTCO groups on advanced device architectures.
2–4 years of industry experience in semiconductor technology analysis, foundry PDK enablement, and PDK component co-optimization such as LVS, DRC, Parasitic Extraction, and Spice models.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or related field.
Strong understanding of CMOS device physics including advanced architectures like GAA, FinFETs, and planar MOSFETs.
Not explicitly mentioned: notice period, explicit onsite or location requirements.
Experienced in PDK design enablement flows with exposure to multiple foundries and technology nodes.
Proficient in physical verification processes (LVS, DRC) and transistor-level Spice modeling, preferably with Cadence-based tool suites.
Collaborative working style, interfacing effectively with core PDK development, technology enablement, and benchmarking teams in advanced semiconductor environments.