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Strong semiconductor brand and metro location, but specialized mixed-signal verification reduces candidate pool.
Highly specialized semiconductor mixed-signal verification skills limit cross-industry transferability.
Explicit senior experience, mandatory SystemVerilog/UVM, EDA tool expertise and mixed-signal verification make filters stringent.
Lead and architect verification strategies for complex digital and mixed-signal designs.
Design and implement advanced UVM-based verification environments and drive coverage closure.
Provide technical mentorship to junior engineers and coordinate cross-functional verification efforts including post-silicon support and customer representation.
7-10+ years of digital design verification experience with emphasis on mixed-signal verification.
Expert-level knowledge of SystemVerilog and UVM for advanced verification architecture.
Proficiency with EDA tools (Cadence/Synopsys), formal verification, and scripting languages (Python, Perl, TCL, Shell).
Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
Experienced verification leader capable of independently solving complex verification challenges and influencing methodology adoption.
Depth in mixed-signal verification combined with strong debugging skills across RTL and gate-level simulations.
Skilled in coordinating cross-disciplinary teams and representing technical solutions to key customers and partners.