STAFF ENGINEER, DDEG Design Methodology
Eightfold AI (company site, opens in a new tab)HyderabadOn-siteDirect career pageEst. 25–45 LPA
Posted on 3 Sept
Reach people at Eightfold AI
People at this company you can reach
Log in to see who works here
Create a free account or log in to see the people at Eightfold AI you could write to:
- Recruiters & HR
- People in this function
- Work addresses
Your match
Against your primary resume
Log in to see your match score
Create a free account or log in to unlock your CV match score across:
- Role fit
- Experience
- Industry relevance
Protocol Intelligence
How competitive this role is
Competition
Background fit
Strictness
Log in to see why each signal reads the way it does.
Job description
Structured overview of role & requirements
About This Role
- Own verification and end-to-end analysis of full-chip gate-level custom DRAM designs with advanced low power and power management technologies across DDR4, LPDDR4, DDR5, LPDDR5 operating up to 6400MT/s.
- Develop, maintain, and run test benches, test cases, and simulation regressions to increase functional coverage for DRAM and emerging memory architectures.
- Leverage AI tools and automation to accelerate verification cycle time, assist test-case development, improve debug efficiency, and validate AI outputs against specifications and simulations.
Minimum Requirements
- Bachelor's or postgraduate degree in Electronics Engineering or related engineering field required.
- Experience with SystemVerilog, UVM Test Bench, and proficiency in digital/mixed signal verification tools and methodologies.
- Experience in verification of DRAM, SRAM, or other memory related fields is required; prior DRAM experience is a plus.
- Work Experience Required: Not explicitly mentioned in the JD.
Ideal Candidate Profile
- Experienced in complex CMOS and gate-level circuit design verification involving digital/mixed signal and AMS verification with co-simulation.
- Able to guide and mentor team members and collaborate effectively with international teams across design and verification domains.
- Strong analytical skills with proficiency in SPICE and/or Verilog simulations, and familiarity with AI-based verification accelerations and scripting (Perl, Python) to build and enhance verification environments.