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Tier-1 brand but niche DRAM verification specialization limits candidate pool.
DRAM/SystemVerilog/UVM verification skills are highly domain-specific and not easily transferable.
Requires specialized SystemVerilog/UVM and DRAM verification expertise, making filters strict.
Own verification and end-to-end analysis of full-chip gate-level custom DRAM designs with advanced low power and power management technologies across DDR4, LPDDR4, DDR5, LPDDR5 operating up to 6400MT/s.
Develop, maintain, and run test benches, test cases, and simulation regressions to increase functional coverage for DRAM and emerging memory architectures.
Leverage AI tools and automation to accelerate verification cycle time, assist test-case development, improve debug efficiency, and validate AI outputs against specifications and simulations.
Bachelor's or postgraduate degree in Electronics Engineering or related engineering field required.
Experience with SystemVerilog, UVM Test Bench, and proficiency in digital/mixed signal verification tools and methodologies.
Experience in verification of DRAM, SRAM, or other memory related fields is required; prior DRAM experience is a plus.
Work Experience Required: Not explicitly mentioned in the JD.
Experienced in complex CMOS and gate-level circuit design verification involving digital/mixed signal and AMS verification with co-simulation.
Able to guide and mentor team members and collaborate effectively with international teams across design and verification domains.
Strong analytical skills with proficiency in SPICE and/or Verilog simulations, and familiarity with AI-based verification accelerations and scripting (Perl, Python) to build and enhance verification environments.