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Tier-1 employer but highly specialized DRAM verification role reduces candidate pool, yielding moderate competition.
Highly specialized DRAM and SV/UVM verification skills limit cross-industry transferability.
Specialized SystemVerilog/UVM and DRAM verification expertise required, making candidate filters stringent.
Own verification and end-to-end analysis of full chip gate-level custom designs with advanced low power and power management technologies across DDR4, LPDDR4, DDR5 and LPDDR5 memory categories.
Leverage AI-based tools and automation frameworks to accelerate verification cycle time, assist in test case and testbench development, and improve debug efficiency across simulation and silicon learning loops.
Develop and maintain verification methodology, test benches and test vectors using simulation tools; collaborate with international teams on developing new verification flows for advanced DRAM and emerging memory products.
Bachelor's or Post Graduate Degree in Electronics Engineering or related field.
Experience with SystemVerilog, UVM Test Bench, and proficient with SPICE and/or Verilog simulations.
Experience in DRAM, SRAM or other memory-related fields is mandatory.
Work Experience Required: Not explicitly mentioned in the JD.
Demonstrated ability to manage complex CMOS and gate-level circuit designs with strong analytical skills.
Experience in digital/mixed signal verification including SV, UVM, and scripting with Perl/Python considered a plus.
Able to review, validate and document AI tool outputs for incorporation into verification plans and debug, indicating a strong judgement and systematic working style.