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Tier-1 metro role with mid-level experience, but niche FPGA/post-silicon skills limit applicant pool.
Highly domain-specific semiconductor and FPGA validation skills restrict cross-industry transferability.
Mandatory 3–5 years plus FPGA/post-silicon, RTL, and scripting requirements enforce strict shortlisting.
Execute and maintain FPGA post-silicon validation plans covering functional, feature, regression, and stress tests.
Develop and maintain design/test automation scripts using Python, Tcl, and C for test execution and regression suites.
Use RTL reading skills and FPGA tools to debug, isolate hardware failures, and collaborate on bug triage and closure.
Bachelor’s or Master’s degree in ECE, EE, Computer Engineering, or related field.
3–5 years of experience in post-silicon validation, FPGA validation, hardware testing, or related hardware domain.
Practical skills in Python for automation, Tcl and C scripting, and ability to read Verilog/SystemVerilog or VHDL RTL for debug.
Familiarity with FPGA flows including compile, program, and basic on-chip debug; lab bring-up experience.
Experienced in hands-on FPGA post-silicon bring-up and lab hardware testing environments.
Skilled in bridging RTL design understanding with hardware failure analysis and debug.
Proficient in automating repetitive test and regression tasks with a methodical, detailed approach to validation.