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Tier-1 employer and Hyderabad metro presence increase candidate density despite specialized DRAM verification skillset.
DRAM, SystemVerilog/UVM and AMS verification create strong industry-specific skill requirements.
Heavy emphasis on SystemVerilog/UVM, DRAM verification, SPICE and specialized skills enforces strict filtering.
Own verification and end-to-end analysis of complex full chip gate level custom DRAM designs, including DDR4, LPDDR4, DDR5, and LPDDR5 operating up to 6400MT/s.
Leverage AI-based tools and automation to accelerate verification cycle times and improve debug efficiency across simulation and silicon learning loops.
Develop and maintain test cases, test benches, and verification flows; collaborate globally with design and verification teams to enhance functional coverage and verification methodologies.
Bachelor's or Post Graduate Degree in Electronics Engineering or related engineering field.
Experience in SystemVerilog, UVM Test Bench, and digital/mixed signal verification tools (e.g., Virtuoso, Xcellium, Simvision, vsim).
Work Experience Required: Not explicitly mentioned in the JD.
Good communication skills and ability to work well in a team; proficiency with SPICE and/or Verilog simulations.
Experienced with DRAM, SRAM, or other memory-related verification, preferably including AMS verification and co-simulation.
Skilled in developing SV testbenches at block and full-chip levels using SV/UVM and scripting (perl, python).
Capable of guiding junior team members and comfortable working with international collaborators on advanced memory design verification challenges.