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Strong employer brand but niche senior CAD/EDA role reduces applicant density.
Highly specialized semiconductor CAD/EDA skillset limits cross-industry transferability.
Explicit 12+ years plus mandatory Cadence, Calibre, scripting, and tape-out experience makes filters strict.
Manage and support industry-standard CAD environments for Microchip FPGA devices including RiscV CPU cores and SOC functionalities.
Collaborate with Engineering Services, Design, and Operations teams to maintain robust design flows and tools, and provide front-line support internally.
Interface with external tool vendors to troubleshoot, resolve issues, and provide guidance; support tape-out activities and foundry interactions.
Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) mandatory.
At least 12 years of relevant experience in CAD tool environment and semiconductor design flows.
In-depth expertise with Cadence full-custom environments (Virtuoso 12, Virtuoso Studio IC 23.1+), physical verification (Mentor Calibre), scripting (SKILL/Perl/Python), and process technologies at 12nm or lower including FinFET.
Travel requirement between 0% to 25%.
Experienced in setting up and debugging advanced semiconductor CAD environments and design automation tools.
Strong cross-functional collaborator capable of coordinating tasks across multiple sites and time zones, reflecting Senior Staff/Technical Staff engineering roles.
Hands-on knowledge of both analog and digital design tools, tape-out procedure, and interaction with foundries and tool vendors, suitable for complex FPGA and SOC development.