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Tier-1 brand and metro location increase competition, but niche senior EDA CAD skillset limits applicant pool.
Requires specialized semiconductor EDA and physical-design experience, making industry transferability low.
Explicit 12+ years and many mandatory EDA tools, process-node, and scripting requirements make filters highly strict.
Own and maintain state-of-the-art CAD tools and design flows for next-generation Microchip FPGA devices with RiscV CPUs and SOC functionality.
Provide frontline support for internal teams using CAD tools and interface with external tool vendors to resolve technical issues.
Develop, test, and automate scripts and tools to aid analog design and participate in tape-out activities and foundry interfacing.
Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
Minimum 12 years of relevant work experience in CAD tool environments, custom design, and process technologies at 12nm or below.
Proficiency in Cadence full-custom design environments (Virtuoso 12, Virtuoso Studio IC 23.1+), scripting languages (SKILL/Perl/Python), and physical verification tools (Mentor Calibre).
Travel flexibility up to 25%.
Experienced with 12nm or lower FinFET process technologies and standard cell library management.
Able to collaborate with cross-functional and cross-geographical teams for tool support and CAD requests.
Skilled in debugging complex CAD, EDA tool issues, and familiar with tape-out workflows in a large semiconductor environment.