DV-Lead Engineer
Quest Global (company site, opens in a new tab)BengaluruOn-siteDirect career pageEst. 18–32 LPA
Posted on 3 Sept
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Job description
Structured overview of role & requirements
About This Role
- Develop and execute verification plans and create reusable UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC designs.
- Verify industry-standard protocols like AXI, AHB, APB, PCIe, USB, Ethernet, DDR, MIPI at various levels including block, subsystem, and SoC.
- Collaborate with RTL designers and validation teams to analyze simulation results, debug issues, and drive verification closure including regression management.
Minimum Requirements
- Experience in creating testcases, stimulus generators, checkers, scoreboards, and coverage models using UVM/SystemVerilog.
- Proven ability to perform functional, code, assertion, and toggle coverage closure along with SystemVerilog Assertions (SVA) development.
- Work Experience Required: Not explicitly mentioned in the JD.
- No explicit mention of mandatory degree, notice period, or location constraints.
Ideal Candidate Profile
- Experienced in complex SoC/IP level verification with hands-on knowledge of industry-standard protocols verification.
- Skilled in building reusable verification environments and improving verification methodologies.
- Able to work collaboratively across design and validation teams to ensure thorough verification and timely closure of design issues.