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Tier-1 brand and Bangalore metro increase competition, but niche FPGA/staff seniority limits applicant pool.
Highly specialized FPGA/ASIC and semiconductor validation skills transfer poorly across other industries.
Role demands specific FPGA, SystemVerilog, prototyping and firmware validation skills, implying strict technical filters.
Develop and maintain Real Number Models (RNM) for Analog/Mixed-Signal IP using SystemVerilog and svreal.
Build and lead FPGA-based prototypes for SoC and system-level validation including pre- and post-silicon firmware validation.
Create Python automation frameworks for simulation, FPGA flows, and CI/CD while driving FPGA prototyping methodology enhancements and mentoring teams.
Bachelor's, Master's, or PhD in Microelectronics, Electrical Engineering, Computer Engineering, or related discipline.
Expertise in ASIC/FPGA design, SystemVerilog, FPGA prototyping, and Python automation.
Knowledge of digital design, FPGA architectures, semiconductor systems, and embedded technologies.
Work experience required: Not explicitly mentioned in the JD.
Experienced in FPGA modeling architecture and firmware validation on FPGA platforms with debugging skills using Vivado ILA and SignalTap.
Strong interdisciplinary collaboration skills working across digital, analog, firmware, and embedded engineering teams globally.
Able to drive faster product validation and accelerate time-to-market through technical leadership and process improvements.