LVS Runset Development Engineer
Intel Corporation (company site, opens in a new tab)10+ yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted on 2 Sept
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Job description
Structured overview of role & requirements
About This Role
- Develop and validate LVS (Layout Versus Schematic) rule decks to ensure design compliance with Intel’s semiconductor process.
- Implement and optimize verification flows across multiple EDA tools like ICV, Calibre, and Pegasus for consistent LVS results.
- Provide debugging support and automation via scripting (Python, SKILL, Tcl, Perl) while collaborating closely with cross-functional teams including PDK, device physicists, and process engineers.
Minimum Requirements
- Experience with LVS runset development is mandatory.
- Proficiency in scripting languages such as Python, Tcl, SKILL, or Perl for automation is required.
- Work Experience Required: Bachelor's degree with 10+ years, or Master's degree with 8+ years, or PhD with 2+ years in LVS runset development or related semiconductor field.
- This role requires on-site presence in Bangalore, India.
Ideal Candidate Profile
- Experienced in advanced technology nodes and semiconductor process verification environments.
- Skilled at multi-tool EDA integration and debugging complex LVS issues within cross-functional teams.
- Comfortable working in a global, collaborative environment with a focus on quality assurance and automation.