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Strong employer brand plus metro location but niche EDA skillset reduces applicant density.
Highly specialized semiconductor and EDA domain experience required, limiting cross-industry transferability.
Role requires specialized EDA/domain skills, tool exposure, and scripting, enforcing strict candidate filtering.
Perform product engineering for Genus Synthesis Solution, focusing on optimizing Power, Performance, and Area (PPA) for digital ASIC designs.
Verify new features within Genus, solve complex problems in physical-aware synthesis to improve logic synthesis and place & route integration.
Provide first-line support to field engineers and customers; ensure interoperability with other Cadence digital logic tools and document product requirements.
Experience in digital design, EDA with emphasis on synthesis, physical design, and timing closure at 20nm or below process nodes.
Prior experience in designer, product engineering, or application engineering roles focused on digital implementation and synthesis.
Proficiency in automation scripting with Perl, Tcl, and shell; knowledge of HDL (Verilog or SystemVerilog) preferred.
Degree: BE/BTech/ME/MS/MTech or equivalent.
Background in digital IC implementation flow with hands-on experience on Cadence tools like Genus and Innovus targeting advanced process nodes (28nm and below).
Strong skills in logic design, timing closure, formal verification, low power design, and physical design, capable of debugging complex design challenges.
Experience interfacing between R&D and customers, capable of root-cause analysis and providing actionable feedback to improve products.