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Tier-1 EDA brand and metro location increase competition, but niche HDL/compiler skillset reduces applicant density.
Highly specialized EDA/compiler skills limit cross-industry transferability.
Role requires specialized C++ HDL compiler and runtime expertise, implying strict technical screening.
Develop and maintain high-quality C/C++ code for HDL language-based compiler and runtime support.
Lead development of HDL compiler front-end for SystemVerilog and VHDL language reference model support.
Improve compiler performance and infrastructure to enhance overall system efficiency.
Proficiency in C/C++ development for compiler and runtime environments.
Experience with HDL compiler front-end development, specifically for SystemVerilog (SV) and VHDL.
Familiarity with compiler performance optimization and infrastructure improvements.
Work Experience Required: Not explicitly mentioned in the JD.
Experienced in cross-geography team collaboration for complex software projects.
Knowledgeable in RTL simulation, synthesis, and runtime environments for hardware description languages.
Capable of handling compiler front-end and performance enhancement in mature HDL compiler projects.