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Tier-1 employer, metro location, and 3–5 year mid-level band, but niche EDA verification skills reduce qualified applicant density.
Highly specialized semiconductor verification expertise is not easily transferable across industries.
Mandatory 3–5 years plus specific ASIC verification skills and EDA tool expertise creates strict filtering.
Own deployment and optimization of Synopsys verification tools (VC SpyGlass, VCS, VC LP, VC Formal, Verdi) for semiconductor design teams in the region.
Lead debugging of complex RTL signoff issues (CDC violations, lint, RDC, low power UPF conflicts, formal property failures) and convert findings into improved verification methodologies.
Drive technical engagements during critical project phases to ensure verification milestones and tapeout schedules are met, collaborating also with R&D to enhance tools.
Bachelor's or Master's degree in Electronics Engineering, Computer Science, or Microelectronics.
3-5 years of industry experience in ASIC design or verification with hands-on RTL verification flow expertise.
Proven skills in RTL signoff flows including linting, CDC, RDC, formal verification, and low power verification using UPF or CPF.
Familiarity with Synopsys EDA tools (VC SpyGlass, VCS, VC LP, VC Formal, FishTail, Verdi) is a strong plus.
Experienced in solving last-minute, complex RTL verification issues close to tapeout with an ability to articulate and implement pragmatic solutions.
Strong collaborator comfortable working across global teams and time zones, aligning stakeholders and managing ambiguity into clear technical plans.
Skilled communicator able to explain complex verification problems (CDC, formal proofs) clearly to design leads and trusted by customers for reliable delivery and support.