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Niche semiconductor EDA skillset but Tier-1 brand and metro location create moderate applicant density.
Specialized semiconductor physical-design and EDA tooling experience is highly industry-specific and not easily transferable.
Explicit senior years, domain-specific tooling and scripting requirements make shortlisting highly selective.
Develop and maintain physical design flows for high performance semiconductor designs.
Collaborate closely with implementation and physical design teams to debug and optimize CAD flows.
Automate and refine physical design methodologies affecting area, power, and timing on latest technologies.
Bachelor's degree with 12 years or Master’s degree with 8 years of relevant experience in physical design or CAD engineering.
Experience with physical design CAD flow including synthesis, place & route, floor planning, and preferably power distribution, static timing analysis, and physical design verification.
Strong scripting skills in TCL/Perl/Makefile for flow automation and development.
Experience with hierarchical place & route, chip finishing issues, and tools such as Cadence Genus, Cadence Innovus, Mentor Calibre is a significant plus.
Experienced in full physical design lifecycle including floorplanning, power distribution, CTS, routing, and chip finishing for advanced process technologies.
Skilled in developing complex P&R algorithms and managing regression flows in a semiconductor design environment.
Comfortable debugging flow issues and collaborating with multi-disciplinary teams to innovate physical design CAD methodologies.