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Medium — Tier‑1 brand and metro location but senior niche EDA specialization limits applicants.
High — specialized semiconductor physical-design and Synopsys tool expertise limits cross-industry transferability.
High — explicit 10+ years requirement plus mandatory Synopsys backend/physical-design tool expertise.
Support sales and adoption of Synopsys products to improve cost, quality, and development time for silicon chip projects.
Provide expertise in Place & Route, Synthesis, and Static Timing Analysis for advanced nodes (sub 5nm) using Synopsys Full RTL-to-GDSII tools (Fusion Compiler, IC Compiler II).
Manage multiple customer activities including product demos, evaluations, training, problem resolution, and participate in account planning with sales teams.
Bachelor's in Electrical Engineering (BSEE) with 10+ years experience or Master's in Electrical Engineering (MSEE) with 7+ years experience.
In-depth experience with Synopsys back-end tools (Fusion Compiler, ICC2, Innovus) and knowledge of ASIC design implementation including Placement, Optimization, CTS, Routing.
Strong understanding of advanced nodes and design methodologies, including physical design and timing closure techniques.
Work Experience Required: 7+ to 10+ years depending on degree. Notice Period: Not explicitly mentioned in the JD.
Experienced engineer with deep expertise in RTL-to-GDSII full flow and multiple Synopsys physical design tools targeting very advanced silicon nodes (sub 5nm).
Capable of managing multiple concurrent customer engagements and collaborating closely with account managers and sales teams.
Familiar with clock tree synthesis methodologies and advanced timing optimization, able to translate customer needs into complex design solutions.