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Mid-level SDE title, metro hiring, and 6+ experience increase applicant density despite niche FPGA/EDA skill requirement.
Specialized FPGA/ASIC EDA and C++ toolchain experience makes background transferability low across industries.
Explicit 6+ years, mandatory C++ proficiency and FPGA/EDA domain preference enforce strict technical shortlisting.
Develop and deliver advanced FPGA software infrastructure supporting a range of FPGA products including small, mid-range, and large FPGAs.
Enhance software capabilities for next-generation FPGA products and maintain existing FPGA design tools.
Engage in requirements analysis, specification writing, unit test planning, and contribute to process improvements and development methodologies.
Bachelor's, Master's, or PhD in Electrical Engineering or Computer Science.
Minimum 6 years of experience in large-scale software development for engineering applications, preferably in FPGA/ASIC EDA domains.
Proficient in C++ with strong object-oriented programming, data structures, algorithms, and graph theory knowledge.
Experience with Linux and Windows platforms is mandatory; scripting knowledge (shell, TCL, Python) and FPGA design knowledge are advantageous but not mandatory.
Experienced in leading engineering software projects in FPGA/ASIC or similar EDA domain environments, showing ability to drive projects independently.
Strong technical proficiency in C++ including modern standards, with hands-on experience across multiple operating systems.
Effective in technical specification, testing planning, and cross-group collaboration, indicating senior-level software development and communication skills.