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Niche EDA place-and-route role with 10+ years seniority yields low competition for qualified candidates.
FPGA place-and-route EDA expertise is highly domain-specific, yielding high background fit sensitivity.
Mandatory 10+ years EDA/place-and-route and C++ expertise creates high shortlisting strictness.
Develop and improve FPGA place and route engine with focus on advanced security workflows like Isolation Design Flow.
Deliver high-performance software solutions optimizing QoR metrics such as performance, area, runtime, and memory usage across multiple FPGA architectures.
Support new FPGA product development, maintain existing tools, and collaborate cross-functionally to build integrated place and route solutions.
10+ years experience in EDA tool development, preferably in place and route.
Proficiency in C/C++, data structures, graph algorithms, logic design, and shell scripting.
Experience in place and route engine development in FPGA or ASIC domain is mandatory; FPGA domain experience preferred.
BS/MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering.
Experienced engineer with strong background in FPGA architecture and place and route engine development for multiple FPGA product lines.
Capable of independently delivering complex software features and quality improvements in a high-performance EDA environment.
Comfortable working in a collaborative team setting with cross-functional coordination and customer support responsibilities.