Senior EDA Engineer – RTL Front End Tools & Methodologies
Lattice Semiconductor (company site, opens in a new tab)4–6 yrsPuneOn-siteDirect career pageEst. 14–22 LPA
Posted on 31 Aug
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Job description
Structured overview of role & requirements
About This Role
- Own RTL front-end EDA methodologies including simulation, power analysis, and constraint validation to ensure scalable, high-quality RTL flows.
- Lead RTL low-power initiatives by defining and enabling power-aware methodologies and supporting power analysis flows using PowerArtist and Joules.
- Develop and maintain automation frameworks in Python and drive adoption of Generative-AI capabilities within EDA tool workflows, collaborating closely with design, verification, and EDA vendor teams on-site in Pune.
Minimum Requirements
- 4-6 years total experience in EDA tools, RTL front-end methodologies, or CAD engineering roles with 3+ years hands-on in RTL power analysis using PowerArtist and Joules.
- Strong proficiency in Python programming for automation of EDA flows.
- Solid understanding of SDC constraints and front-end timing concepts.
- Location requirement: Pune, India (Non-negotiable) with mandatory 4 days/week in office hybrid work model.
Ideal Candidate Profile
- Experienced in driving RTL low-power initiatives and early power efficiency improvements at RTL level.
- Demonstrates expertise in RTL simulation/debug using QuestaSim, Synopsys VCS, and Cadence Xcelium and in constraint validation.
- Comfortable interfacing with EDA vendors and leading technical issue resolution and tool roadmap alignment in a cross-functional global environment.