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Niche EDA requirement reduces applicants despite mid-level title, Pune metro, and 2+ years experience.
Specialized EDA/place-and-route and FPGA expertise limits cross-industry transferability.
Mandatory EDA place-and-route experience, C++ skills, and degree requirement enforce strict shortlisting.
Design and develop FPGA place and route engine software to improve quality, performance, area, runtime, and memory utilization.
Develop new features and capabilities for place and route tools supporting multiple FPGA product lines including new FPGA product support.
Create and maintain unit tests and collaborate cross-functionally to deliver integrated FPGA design software solutions.
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or Computer Engineering.
Proficient in C/C++, data structures, graph algorithms, logic design, and shell scripting.
Experience in place and route engine development in FPGA or ASIC domain is mandatory.
2+ years of experience in EDA tool development, preferably place and route tools.
Demonstrated ability to improve and develop FPGA place and route engine features with measurable impact on design quality and efficiency.
Experience working in multi-disciplinary teams delivering software for FPGA architectures, showing collaboration and communication skills.
Background in FPGA architectures and multiprocessing development is advantageous for success in this role.