Sr Staff Software Development Engineer(C++, EDA, Place & Route)
Lattice Semiconductor (company site, opens in a new tab)12+ yrsPuneOn-siteDirect career pageEst. 35–55 LPA
Posted on 31 Aug
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Job description
Structured overview of role & requirements
About This Role
- Lead development and quality improvement of FPGA place and route engine, focusing on optimization of metrics such as performance, area, runtime, and memory across multiple FPGA architectures.
- Develop advanced security flows like Isolation Design Flow and support new Lattice FPGA product lines.
- Create unit tests, maintain existing tools, and collaborate cross-functionally to deliver integrated FPGA design software solutions.
Minimum Requirements
- 12+ years of experience in EDA tool development, preferably in place and route engine for FPGA or ASIC.
- Degree in Electrical Engineering, Computer Science, or Computer Engineering (BS/MS/PhD).
- Proficient in C/C++, data structures, graph algorithms, logic design, and shell scripting.
- Experience in FPGA place and route engine development is required; multi-processing development and knowledge of FPGA architectures are pluses.
Ideal Candidate Profile
- Extensive hands-on experience in FPGA place and route engine development with strong algorithmic and data structure skills.
- Capable of independently driving feature development and quality improvements in complex EDA tools.
- Strong collaboration and communication skills to work effectively with cross-functional teams and support customer needs.