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Niche EDA place-and-route specialization and seniority lowers qualified applicant density.
Highly specialized FPGA/EDA expertise limits transferability across industries.
Explicit 12+ years and mandatory EDA/place-and-route experience create stringent screening filters.
Lead development and quality improvement of FPGA place and route engine, focusing on optimization of metrics such as performance, area, runtime, and memory across multiple FPGA architectures.
Develop advanced security flows like Isolation Design Flow and support new Lattice FPGA product lines.
Create unit tests, maintain existing tools, and collaborate cross-functionally to deliver integrated FPGA design software solutions.
12+ years of experience in EDA tool development, preferably in place and route engine for FPGA or ASIC.
Degree in Electrical Engineering, Computer Science, or Computer Engineering (BS/MS/PhD).
Proficient in C/C++, data structures, graph algorithms, logic design, and shell scripting.
Experience in FPGA place and route engine development is required; multi-processing development and knowledge of FPGA architectures are pluses.
Extensive hands-on experience in FPGA place and route engine development with strong algorithmic and data structure skills.
Capable of independently driving feature development and quality improvements in complex EDA tools.
Strong collaboration and communication skills to work effectively with cross-functional teams and support customer needs.