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Highly specialized principal-level semiconductor verification reduces candidate density despite Tier-1 brand.
Very specific semiconductor verification protocols and SoC expertise limit cross-industry transferability.
Explicit 20+ years, leadership, and specialized HDL/UVM/formal requirements create stringent filters.
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Lead end-to-end design verification for complex SoCs and subsystems from planning through signoff.
Develop and execute advanced verification methodologies including UVM-based testbenches, formal verification, and power-aware verification for multiple product business units.
Collaborate cross-functionally with architecture, emulation, FPGA, firmware, and software teams to ensure full-system verification readiness and innovation in verification strategies.
20+ years of experience in digital pre-silicon verification with leadership roles in IP, subsystem, or SoC-level digital verification.
Strong expertise in Verilog/SystemVerilog, UVM methodology, functional and code coverage closure, NoC/interconnect verification, and power-aware verification (UPF).
Proficiency in formal verification, protocol verification (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3), and test planning using constrained-random verification and assertions.
Work Experience Required: 20+ years in digital pre-silicon verification; Degree: B.Tech/M.Tech in relevant discipline.
Senior engineering leader skilled at driving architecture and execution of scalable, advanced SoC verification methodologies across multiple teams and product lines.
Experienced in managing complex projects involving cross-domain collaboration including AI/ML accelerators, processor-based systems (ARM, RISC-V), and mixed-signal integration.
Demonstrated ability to innovate verification strategies, lead technical initiatives, and influence global teams with a strong problem-solving orientation.