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Tier-1 brand and mid-level metro role present, but niche DDR specialization lowers applicant density.
Highly specialized DDR driver and firmware expertise limits cross-industry transferability.
Explicit 4-8 years plus mandatory low-level DDR/driver and debugging skills create strict filtering.
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Own debugging and development of DDR initialization and runtime driver sequences for LP4x/LP5x DDR technology.
Drive multiple chipset programs focusing on DDR technology, collaborating with cross-functional teams to resolve system-level issues (e.g., bit flips, memory corruption).
Analyze extensive data to identify patterns and enhance test cases for DDR stability, power, and performance validation.
4-8 years work experience in Embedded Systems and DDR domain.
Bachelor's or higher degree in Engineering or related fields (ECE, EEE, E&I, CSE, IT) relevant to embedded systems and DDR.
Strong programming skills in C and Python, with knowledge of Embedded Systems, JTAG, processor and CPU architecture, RTOS, and BSP driver development/debugging.
Relevant experience in DDR technology including memory controllers, PHYs, DRAMs, firmware, platform driver development, or board bring-up required.
Experienced in system-level debugging and validation for DDR memory systems within SoC architectures.
Comfortable working across hardware and software teams to diagnose and resolve complex DDR and memory subsystem issues.
Skilled in handling multiple chipsets and driving programs through various product quality stages from development to commercial launch.