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Tier-1 employer, metro location, mid-level experience increases applicant density despite niche EDA specialization.
Highly domain-specific PDK and EDA tooling expertise limits cross-industry transferability.
Mandatory 6+ years PDK development, Cadence SKILL/Python and EDA tool expertise creates strict filters.
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Develop and test QA framework for validation of Process Design Kits (PDKs) for semiconductor process technologies.
Develop PDK components including device level layout generators (PCELLs), physical verification rules (DRC/LVS), and parasitic extraction flows.
Collaborate with design teams, device modeling, process development, and foundry groups; provide technical CAD support and interact with EDA software vendors for tool enhancements.
Minimum 6 years of experience in PDK development and automation programming.
Proficient in Python and Cadence Skill Language; knowledge of Perl, Tcl, Bash is a plus.
Bachelor's or Master's in Electrical or Computer Engineering with emphasis on IC design and semiconductor processes.
Location: Bangalore, India; willingness to travel approximately 10%; export licensing review may apply for non-US citizens.
Experienced in developing and automating PDK validation workflows for analog, mixed-signal, RF, and digital semiconductor technologies.
Strong programming skills in Python and scripting languages alongside deep understanding of physical verification (DRC/LVS) and parasitic extraction processes.
Capable of working independently within engineering enablement to interface across design, process, device modeling, and vendor teams for CAD tool and methodology improvements.