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Strong employer and metro location but niche EDA skills limit applicant pool.
High — specialized EDA and advanced-node physical design skills are industry-specific and not easily transferable.
High — explicit 7-12 years and mandatory EDA/advanced-node physical-design experience required.
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Improve power, performance, and area (PPA) on critical customer chip designs using Cadence tools.
Manage benchmarking and customer communication regarding design issues and progress.
Collaborate with R&D teams to influence software tool development for advanced chip design platforms.
7-12 years of experience in chip physical design or related field.
Strong knowledge of physical design flow from netlist to GDSII, including floorplanning, power planning, placement, clock tree synthesis and routing.
Experience working with low technology nodes 7nm or below; experience with 3nm or 2nm technology is a plus.
Bachelor's or Master's degree in Engineering or equivalent.
Expertise in timing, congestion, power optimization, routing, and DRCs debugging for advanced semiconductor nodes.
Ability to multitask across different design issues and coordinate with diverse teams including R&D and customer engagement.
Experience working in a customer-facing role managing benchmarks and progress communication.