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Tier-1 brand, metro location and mid-level seniority increase competition, but niche UVM/IP skillset limits applicant pool.
Highly specialized semiconductor IP verification skills reduce cross-industry transferability.
Explicit 4+ years requirement and mandatory UVM/SystemVerilog IP verification skills enforce stringent shortlisting.
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Own the pre-silicon verification of IP modules and subsystems, including defining and executing verification plans based on specifications.
Architect, develop, and debug UVM-based verification environments, create test cases, and run simulations across multiple platforms (RTL, gate level, FPGA, emulation).
Interface with hardware, firmware, software, architecture, and system engineering teams to ensure comprehensive verification coverage and functionality understanding.
Bachelor's degree in Electrical Engineering or Computer Science.
4+ years of experience in IP or subsystem verification.
Proven expertise in testbench design and development using UVM methodology for IP/Subsystem and SoC.
Strong skills in Verilog, SystemVerilog, C/C++, Shell scripting and proficiency in metric-driven verification, functional and code coverage.
Experienced in using directed and constrained random methodologies with strong knowledge of formal verification and assertions.
Comfortable with debugging designs pre- and post-silicon in both simulation and hardware environments.
Capable of collaborating across multiple engineering disciplines and communicating complex technical details effectively.