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Tier-1 brand and Bangalore location increase competition, but niche EDA/ML specialization limits candidate pool.
Requires semiconductor EDA and ASIC design domain knowledge, reducing cross-industry transferability.
Explicit five-year requirement plus mandatory AI/ML and software skills increases filtering rigor.
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Develop and prototype AI/ML-based automation tools to improve ASIC design and implementation efficiency and quality (power, performance, area, verification) for SoC/IP teams.
Collaborate with architecture, IP design, SoC design, verification, implementation, and design enablement teams to pilot these AI/ML-driven methodologies in production designs.
Engage with AI/ML research communities and leverage cutting-edge techniques (GenAI, Reinforcement Learning, Graph Neural Networks) to transform VLSI CAD software for advanced node SoC development.
Bachelor's or Master's in Computer Science, Electrical Engineering, Computer Engineering or related fields with strong software development background.
Minimum 5 years experience in complex software development projects.
Proficiency in Python and C++ programming; Unix/Linux environment experience; familiarity with revision control tools like Git and BitBucket.
Strong AI/ML expertise and demonstrated hands-on software development skills.
Experience in VLSI CAD methodology, EDA tools for design, verification, DFT, and implementation strongly favored.
Expertise in design constraints and flows including SDC, clocks, CDC, RDC, static timing analysis, low-power and power-aware flows like UPF.
Familiarity with software development tools and processes such as Jenkins, LSF, CI/CD, and design revision control systems (GIT, DesignSync) to support automation projects.