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Tier-1 semiconductor brand and Bangalore location increase visibility despite niche EDA skillset.
Specialized EDA, DFT, and nanometer tapeout expertise limits cross-industry transferability.
Multiple mandatory EDA, DFT, synthesis, tool and scripting requirements create strict resume filters.
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Develop and lead Design-for-Test (DFT) methodologies for corporate-wide digital flows using Siemens and Cadence EDA tools.
Collaborate with global CAD methodology teams to automate and integrate CAD flows for centralized deployment.
Provide technical expertise and consultation on DFT and front-end design EDA flows to support successful tapeouts of multi-million gate SoC products.
5+ years of experience in CAD methodology related to digital design-for-test and synthesis.
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or Microelectronics.
Proficient in Siemens, Cadence, or Synopsys EDA tool suites with expertise in digital implementation flows from RTL to GDSII in advanced nanometer technologies.
Willingness to travel up to 10%; location Bangalore (ADBL).
Demonstrated track record of involvement in successful multi-million gate SoC design tapeouts using nanometer and FinFET technologies.
Strong skills in automating CAD methodologies using TCL, Python, PERL, and Tk, plus experience debugging vendor EDA tool issues.
Experience working in a global development environment collaborating across design and CAD teams.