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Job Description
Structured overview of role & requirementsAbout This Role
Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations such as ESD paths, current density, voltage stress, and floating gates.
Integrate and optimize verification flows across multiple EDA tools including Calibre PERC (preferred), Cadence Pegasus, and Synopsys to ensure consistent results.
Collaborate with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules and provide expert support in debugging PERC violations.
Minimum Requirements
Experience in PERC rule development, preferably with Calibre PERC.
Proficiency in scripting languages including Python, SKILL, Tcl, or Perl for automation.
Bachelor’s degree with 10+ years, or Master’s degree with 8+ years, or PhD with 2+ years in Electrical, Computer, or Electronics Engineering.
This role requires on-site presence in Bangalore, India.
Ideal Candidate Profile
Strong expertise in electrical reliability verification focusing on ESD, latch-up, and related failure mechanisms.
Experience working with advanced semiconductor technology nodes and multi-EDA tool environments.
Ability to work cross-functionally with global teams and translate complex reliability requirements into automated rule decks.