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Tier-1 employer plus metro location but niche silicon validation skills reduce general applicant density.
Specialized silicon validation and RTL expertise is highly industry-specific and not widely transferable.
Explicit years, mandatory C++, RTL, hardware-software co-design and architecture knowledge make filters highly restrictive.
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Develop and integrate functional and performance simulation models for Machine Learning (ML) IPs within Cloud TPU SoC architecture.
Collaborate with pre-silicon verification and post-silicon validation teams to incorporate models into validation workflows.
Work cross-functionally with compiler and software teams to advance development activities through early feature enablement.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
At least 2 years of experience developing simulation models for hardware IPs, or a PhD.
Proficiency in modern C++ software system development.
Experience or understanding of ML IP instruction sets and architecture relevant to silicon validation is implied but not explicitly listed.
Advanced degree (Master's or PhD) with emphasis on computer architecture, processor, or accelerator design.
Experience in hardware and software co-design and mapping ML models to hardware architectures.
Comfortable working at the intersection of hardware architecture, software development, and validation processes in a hyperscale computing environment.