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Job Description
Structured overview of role & requirementsAbout This Role
Own and support scalable digital verification infrastructure including regression, automation frameworks, and CI/CD systems to improve tapeout timelines.
Serve as primary CAD support liaison for design and verification teams troubleshooting simulation, coverage, regression, and debug tool issues.
Collaborate with EDA vendors and cross-functional teams to deploy and optimize verification tools, environments, and methodologies including UVM and coverage-driven techniques.
Minimum Requirements
Bachelor’s or Master’s degree in Electronics Engineering.
12+ years of experience in Digital Verification, CAD, or Engineering Support roles.
Proficiency with digital verification flows, System Verilog, UVM, scripting languages (Python, Tcl, Perl), Linux environments, and EDA tools like VCS, Xcelium, Verdi, vManager.
Experience managing regression environments, CI/CD systems, and compute farm resource optimization.
Ideal Candidate Profile
Experienced in complex digital verification flows with hands-on debugging and tool support expertise.
Strong collaborator able to coordinate across global, multi-cultural teams and liaise with EDA vendors effectively.
Knowledgeable in modern verification methodologies and interested in adopting AI/ML-enabled verification tools and automation strategies.