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Job Description
Structured overview of role & requirementsAbout This Role
Own the complete verification lifecycle of next-generation SoCs/IPs including testplan creation, environment development, debugging, and coverage closure.
Develop scalable and reusable constrained-random verification environments using SystemVerilog and UVM methodology.
Drive verification closure by defining and analyzing functional and code coverage to achieve 100% coverage targets.
Minimum Requirements
5+ years of ASIC/SoC Design Verification experience.
Strong expertise in SystemVerilog and Universal Verification Methodology (UVM).
Bachelor's or Master's degree in ECE, EEE, Embedded Systems, or VLSI.
Right to work in India with successful background and export control clearances as applicable.
Ideal Candidate Profile
Experienced in debugging complex RTL/testbench issues using industry tools like Verdi or DVE.
Proficient in digital logic fundamentals including pipelines, memory controllers, and clock/reset domain handling.
Capable of mentoring juniors and collaborating effectively with Design, Architecture, and Validation teams.