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Tier-1 brand and Bangalore metro increase competition, though ASIC methodology niche lowers applicant density.
Highly specialized ASIC integration and methodology expertise limits transfer across industries.
Explicit 2+ years, mandatory ASIC methodology experience, and scripting/flow skills make filters strict.
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Own the full-chip and block-level integration process for multiple NVIDIA SoC and GPU projects, ensuring seamless connectivity and hierarchy management.
Define, evolve, and implement ASIC design methodologies to improve scalability, quality, and turnaround time across diverse silicon platforms.
Build and maintain automation pipelines (using Python/Perl) to streamline integration, debugging, delivery processes, and collaborate cross-functionally to ensure flow compatibility and design readiness.
Bachelor’s or Master’s degree in EE, ECE, CS, or equivalent.
Minimum 2 years of experience in ASIC design integration and methodologies.
Strong understanding of IP development and build flows for ASIC design.
Work Experience Required: 2+ years in ASIC design integration and methodologies.
Experienced in managing complex SoC/GPU ASIC full-chip and block-level integrations across multiple projects and technology nodes.
Skilled in automation scripting (Python/Perl) and building modular, reusable design infrastructure for diverse architectures.
Able to collaborate effectively with global, cross-cultural teams, and influence multiple stakeholders for methodology definition and adoption.