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Tier-1 brand and metro location increase competition, but specialized DV skills and senior level limit candidate pool.
Highly domain-specific semiconductor DV skills (UVM/SystemVerilog, SoC protocols) limit cross-industry transferability.
Mandatory 8+ years and specific UVM/SystemVerilog and IP verification expertise create strict shortlisting filters.
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Own verification test benches and associated verification collateral for Infrastructure IPs such as DDRSS and Memory Controllers used in SoCs for various devices.
Plan and implement IP/Cluster/Formal verification flows and coordinate with Design and SoC teams throughout the IP development lifecycle.
Lead efforts on test planning, debugging regressions, coverage closure, quality sign-off, and post-silicon debug involving Design, Software, and test teams.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years experience OR Master's degree with 3+ years experience OR PhD with 2+ years experience in Hardware Engineering or related domain.
8 years of experience in IP verification or related field mentioned specifically for this role.
Strong expertise in UVM based verification methodology and knowledge of ARM bus protocols, Virtual Memory concepts, and SoC system architecture.
Experience in developing verification components like Monitors, Scoreboards, Sequencers using SystemVerilog, UVM, and scripting languages for automation.
Experienced Verification Architect/Engineer with deep domain expertise in Infrastructure IPs verification for SoCs targeting smartphones, tablets, and similar devices.
Skilled in coordinating multi-team efforts including System Architects, Design, Emulation, and SoC level performance teams.
Proficient in debugging and root cause analysis, including post-silicon bring-up and familiarity with silicon debug tool chains, plus automation scripting ability in Python or Perl.