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Tier-1 brand and Bangalore location increase applicant density despite niche specialization and senior requirement.
Highly specialized semiconductor PDK and EDA validation skills limit cross-industry transferability.
Mandated 12+ years and specific EDA tools, scripting, and PDK expertise make filters highly selective.
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Develop and maintain Process Design Kit (PDK) collateral and design verification decks for advanced technology nodes, focusing on parasitic extraction, LVS, and physical verification.
Validate PDK libraries and perform device modeling, test structure building, and simulations to ensure compliance and quality across design environments.
Collaborate with design and manufacturing teams, EDA vendors, and cross-functional groups to resolve PDK issues, automate QA processes, and improve design toolflows.
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 12+ years experience; or Master's with 10+ years; or PhD with 8+ years in PDK development and validation.
Proficiency in physical verification tools such as Calibre, Pegasus, or ICV, and parasitic extraction tools like StarRC or QRC.
Experience with scripting languages (Python, TCL, or PERL) for automation.
Work Experience Required: Minimum 8 years in PDK development and validation.
Experienced engineer comfortable operating at the intersection of PDK development, device modeling, and physical verification methodologies for advanced semiconductor process nodes.
Demonstrates ability to manage complex verification workflows and collaborate effectively with cross-functional teams and external EDA vendors to enable new tool capabilities.
Skilled in automating QA methodologies and optimizing design flows to support scalable, high-quality silicon design environments.