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Tier-1 employer and Bangalore location, but niche specialized skillset reduces applicant density.
Highly domain-specific semiconductor EDA and DRC expertise limits cross-industry transferability.
Explicit 10+ years requirement and mandatory EDA tools and scripting skills enforce strict filters.
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Develop, maintain, and optimize DRC runsets/rule decks for advanced semiconductor process nodes using physical verification tools like Calibre, ICV, and Pegasus.
Create and validate complex design rule checks and test cases to ensure runset functionality, coverage, and correctness.
Automate and improve runset development, validation, and deployment processes while supporting production users and debugging issues.
10+ years experience with Bachelor's or 8+ years with Master's in Electronics, VLSI, Computer Engineering, or related field.
Strong expertise in DRC rule deck/runset development and debugging for semiconductor technology nodes.
Hands-on experience with physical verification tools Siemens Calibre, Synopsys ICV, or Cadence Pegasus.
On-site work requirement in Bangalore, India.
Experienced in semiconductor manufacturing processes, layout design rules, and physical verification methodologies.
Proficient in programming/scripting languages such as Python, Perl, Tcl, and Shell for automation purposes.
Capable of working cross-functionally with process developers, CAD teams, and design stakeholders in a fast-paced, dynamic environment.