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Tier-1 brand, mid-level (4+ yrs), Bangalore metro—high applicant competition despite niche specialization.
Highly specialized semiconductor physical-verification and PDK expertise limits cross-industry transferability.
Requires specific DRC/Calibre expertise and 4+ years experience, creating strict screening filters.
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Develop, maintain, and optimize DRC runsets/rule decks for advanced semiconductor process nodes using industry-standard physical verification tools.
Translate process design rules into efficient physical verification checks and validate rule deck functionality with comprehensive test cases.
Debug and resolve DRC rule deck issues, improve runset quality and runtime, and support production users in a fast-paced, on-site environment.
4+ years experience with a Bachelor's or 2+ years with a Master's degree in Electronics, VLSI, Computer Engineering, or related field.
Strong experience in DRC rule deck/runset development and physical verification tools such as Siemens Calibre, Synopsys ICV, or Cadence Pegasus.
Hands-on expertise in debugging and optimizing DRC checks and scripting skills in Python, Perl, Tcl, or Shell.
On-site presence required in Bangalore, India (Shift 1).
Expertise in semiconductor process technology and physical verification tools, capable of handling complex geometric and connectivity rule development.
Experience collaborating with process developers, design rule owners, CAD/EDA teams, and design groups to deliver production-quality solutions.
Ability to apply automation and AI-based tools to enhance rule deck development and validation efficiency.