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Tier-1 brand, mid-level experience and Bangalore metro increase competition, though specialized hardware verification skills limit applicant pool.
Highly specialized ASIC/SoC verification skills limit transferability across non-semiconductor industries.
Mandatory 2+ years plus specific SV/UVM and ARM/AXI protocol skills enforce moderate filtering.
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Own unit level verification of HSIO IP in automotive chips, focusing on ARM-based distributed fabric for control, sidebands, and data transport.
Develop UVM-based test benches, verification methodologies, and reusable verification components such as bus functional models, monitors, and scoreboards.
Drive verification closure by defining test plans, implementing functional coverage, and collaborating with architects, designers, FPGA, and post-silicon teams.
BTech or MTech in ECE, EE, CSE, or equivalent degree.
Minimum 2+ years experience in unit, sub-system, or SoC level verification closure.
Proven experience with ARM architecture and protocols (AXI, AHB, APB).
Experience with SystemVerilog (SV) and UVM verification methodologies.
Experienced in complex verification projects involving CPU, memory sub-systems, and NOC-based interconnect fabric within automotive or related semiconductor domains.
Comfortable working in a matrix organization collaborating across architects, designers, FPGA, and global teams.
Has exposure or interest in AI-assisted code development and possibly formal verification to improve verification efficiency and automation.