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Tier-1 employer but senior, specialized verification role reduces generalist applicant density.
Highly domain-specific semiconductor verification skills limit cross-industry transferability.
Explicit 12+ years and mandatory SystemVerilog/UVM and DDR verification expertise enforce strict filters.
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Lead architecture and implementation of verification methodology for next-generation DDR memory designs with UVM-based testbenches.
Develop verification plans, coverage strategies, and sign-off criteria while collaborating closely with build teams to ensure verification completeness and quality.
Leverage AI/ML tools to enhance verification efficiency, regression analysis, and failure classification, and mentor verification engineers on advanced methodologies.
Minimum 12 years in Design Verification; experience with DDR/GDDR/DDR memory verification preferred.
Expert-level proficiency in SystemVerilog, UVM, and advanced verification methodologies required.
Bachelor’s, Master’s, or PhD degree (or equivalent experience) in Electrical Engineering, Computer Engineering, or related field.
Experience with AI/ML concepts related to verification optimization and scripting languages like Python/TCL/Perl for automation.
Senior verification professional with proven leadership in driving technical verification direction and mentoring teams.
Strong background in memory (DDR/GDDR) verification with hands-on experience in mixed-signal verification and AMS Co-Simulation techniques (preferred).
Experienced in applying data-driven and AI-assisted approaches to improve verification processes and predictive failure analysis.