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Tier-1 employer and metro location increase applicant density, but specialized ASIC/UVM skills limit competition.
Specialized ASIC verification tools and languages limit cross-industry transferability.
Mandatory 3+ years and hard skills (SystemVerilog, UVM, simulators, scripting) create strict screening.
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Develop and maintain ASIC verification environments using SystemVerilog and UVM methodologies, covering block, subsystem, and full-chip levels.
Create and execute comprehensive verification test suites, perform functional verification, analyze code and functional coverage, and support gate-level simulations.
Collaborate closely with RTL designers and software/firmware teams to debug and resolve design issues and improve verification productivity with scripting automation.
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field (BSEE/MSEE).
Minimum 3 years of experience in ASIC/SoC verification.
Strong expertise in SystemVerilog and UVM/OVM/VMM verification methodologies, with hands-on experience in constrained-random verification techniques.
Experience with industry-standard simulators such as VCS or NC/Xcelium and scripting skills in Perl, Tcl, Python, or Shell.
Experienced in independently verifying complex ASIC blocks and driving them to tape-out signoff.
Comfortable working onsite primarily at HPE office in a cross-functional environment with design and software teams.
Skilled in debugging, root-cause analysis, and advancing verification methodologies with automation and infrastructure improvements.