Back
Tier-1 brand but highly specialized DRAM verification principal role reduces candidate density.
Highly specialized semiconductor verification skills limit cross-industry transferability.
Requires niche SystemVerilog/UVM and DRAM verification expertise, making hiring filters strict.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own verification and end-to-end analysis of full chip gate level custom DRAM designs with advanced low power and power management technologies across DDR4, LPDDR4, DDR5, and LPDDR5.
Leverage AI-based tools and automation to accelerate verification cycles, assist in test-case/testbench development, and enhance debug efficiency across simulation and silicon loops.
Collaborate with design/verification teams globally to develop verification methodologies, flows, and environments, handling multi-functional tasks to increase functional coverage and debug.
Bachelor's or Post Graduate Degree in Electronics Engineering or related engineering field required.
Experience with SystemVerilog, UVM Testbench, digital/mixed signal verification, and simulation tools such as Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice.
Work Experience Required: Not explicitly mentioned in the JD.
Good communication and teamwork skills, plus analytical capability for complex CMOS and gate level circuit designs, proficiency with SPICE and/or Verilog simulations.
Experienced in DRAM, SRAM or other memory-related fields with familiarity in AMS verification and co-simulation.
Ability to guide new team members and collaborate internationally, showing strong judgment in validating AI outputs for verification/test processes.
Hands-on skills in building SV testbenches at block and full chip level, scripting (Perl, Python), and writing Verilog/Real Number Models for enhanced verification coverage.